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W523AXXX
HIGH FIDELITY PowerSpeechTM
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 BLOCK DIAGRAM ...................................................................................................................... 3 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION.................................................................................................... 5 5.1 5.2 5.3 5.4 6. 6.1 6.2 6.3 7. 8. Register Definition and Control........................................................................................ 5 Option Control Function................................................................................................... 8 Interrupt Vector Allocation ............................................................................................... 8 CPU Interface ................................................................................................................ 10 Absolute Maximum Ratings........................................................................................... 13 DC Characteristics......................................................................................................... 13 AC Characteristics......................................................................................................... 14
ELECTRICAL CHARACTERISTICS......................................................................................... 13
BONDING PAD DIAGRAM ....................................................................................................... 15 TYPICAL APPLICATION CIRCUIT........................................................................................... 17 8.1 8.2 DAC Output ................................................................................................................... 17 PWM Output .................................................................................................................. 18
9.
REVISION HISTORY ................................................................................................................ 19
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Publication Release Date: May 20, 2003 Revision A3
W523AXXX
1. GENERAL DESCRIPTION
The W523AXXX family are programmable speech synthesis ICs that utilize Winbonds new high fidelity voice synthesis algorithm to generate all types of voice effects with high sound quality. The W523AXXX's LOAD, JUMP, MOVE and INC commands and ten programmable registers provide powerful user-programmable functions that make this chip suitable for an extremely wide range of speech IC applications. The W523AXXX family includes 14 kinds of part numbers with same function except for the voice duration shown below:
PART NO. Duration PART NO. Duration W523A008 8 sec. W523A040 40 sec. W523A010 10 sec. W523A050 50 sec. W523A012 12 sec. W523A060 60 sec. W523A015 15 sec. W523A070 70 sec. W523A020 20 sec. W523A080 80 sec. W523A025 25 sec. W523A100 100 sec. W523A030 30 sec. W523A120 120 sec.
Note: The voice duration is estimated by various sampling rate.
2. FEATURES
* * * * * * * Operating voltage range: 2.4 - 5.5 volts New high fidelity synthesis algorithm Either PWM mode or D/A converter mode can be selected for AUD output Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs Two trigger input debounce times (50 mS or 400 uS) can be set Provides up to 2 LEDs and 5 STOP outputs Flexible functions programmable through the following: - LD (Load), JP (Jump), MV (Move) and INC (Increase) commands - Four general purpose registers: R0, R1, R2 and R3 - Six special purpose registers: EN0, EN1 (excludes W523A008 and W523A010), MODE0, MODE1, STOP and PAGE - Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6 for W523A012 ~ W523A120; n=1,2,3 or 4 for W523A008 and W523A010 - Speech equations - END instruction * * * * Supports CPU interface operation Symbolic compiler supported Instruction cycle 400 S typically Section control for - Variable frequency: 4.8/6/8/12 KHz - LED: ON/OFF * Up to 256 voice groups can be used in single page mode; or extended to 2,048 voice groups in multi page mode, such as 8-page, 16-page and 32-page.
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W523AXXX
3. BLOCK DIAGRAM
OSC VDD1 RESET TEST TG1 TG2 *TG5 *TG6 VSS1 LED1 CONTROLLER PWM DRIVER D/A CONVERTER SPEECH SYNTHESIZER TIMING GENERATOR ROM
*: TG3, TG4 for W523A008 and W523A010
STPA/BUSY
STPB
LED2/STPC
STPD
STPE -3-
VSS2
VDD2
Publication Release Date: May 20, 2003 Revision A3
SPK+/AUD
SPK-
W523AXXX
4. PIN DESCRIPTION
NAME OSC VDD1 TEST
RESET
I/O I I I I I I I O O O O O O O O Ring oscillator input Positive power supply
DESCRIPTION
Test pin. Internally pulled low Active low to reset all devices as POR function. Internally pulled high. Direct trigger input 1. Internally pulled high Direct trigger input 2. Internally pulled high Direct trigger input 5. Internally pulled high Direct trigger input 6. Internally pulled high Negative power supply LED1 output Stop signal A or Busy signal Stop signal B LED2 output or Stop signal C Stop signal D Stop signal E PWM output Current type output or PWM output for speaker Negative power supply Positive power supply
TG1 TG2 *TG5 *TG6 VSS1 LED1 STPA/BUSY STPB LED2/STPC STPD STPE SPKAUD/SPK+ VSS2 VDD2
*: TG3, TG4 for W523A008 and W523A010
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W523AXXX
5. FUNCTIONAL DESCRIPTION
I/O pins: The W523AXXX family provides up to 4 trigger pins, which can be extended to 24 matrix trigger inputs, up to 5 STOP output pins and up to 2 LED output pins. All of these I/O pins' status can be easily defined by PowerSpeech program. Powerful programmable features: The W523AXXX family provides JUMP (JP), LOAD (LD), MOVE (MV), INC, and END commands and 10 programmable registers, such as R0 ~ R3, EN0, EN1, MODE0, MODE1, STOP and PAGE, can be easily used to program the desired playing mode, stop output signal form, LED flash type, and trigger pin interrupt modes. The chip's programmable features can also be used to develop new, customized functions for a wide variety of innovative applications. Programmable Power-on Initialization: Whenever the W523AXXX is powered on or pressed the RESET pin, the program contained in the 32nd voice group will be executed after the power-on delay (about 160 mS), so the user can write a program into this group to set the power-on initial state. If user does not wish to execute a program at power-on, an "END" instruction should be entered in the group 32. The interruption priority is shown as below while other trigger pins as well as JUMP (JP) command are executing simultaneously during POI executing period: POI > TG1F > TG1R > TG2F > TG2R > *TG5F > *TG5R > *TG6F > *TG6R > "JP" instruction. *: TG3, TG4 for W523A008, W523A010
5.1
Register Definition and Control
The register file in the W523AXXX family is composed of 10 registers, including 4 general-purpose registers and 6 special purpose registers. They are defined to facilitate the operations for various purposes. The default setting values of the registers are given in the following table. REGISTER General Register Special Register R0-R3 EN0 (W523A008~A010) EN0 (W523A012~A120) EN1 (W523A012~A120) MODE0, MODE1 STOP PAGE NAME DEFAULT SETTING 00100000B 11111111B XX11XX11B XX11XX11B 11111111B XXX11111B 00000000B
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W523AXXX
5.1.1
BIT 7 6 4 2 5,3,1,0
MODE0 Register
DESCRIPTION LED mode LED2/STPC pin selection Debounce time STPA/BUSY pin selection X 1: Flash 0: DC 1: LED2 output 0: STPC output 1: Long 0: Short 1: STPA output 0: BUSY output Don't care DEFINITION
The MODE0.7 bit defines the output type of LED1 and LED2 pins as Flash output (3 Hz) or DC output. The MODE0.6 bit defines the configuration of LED2/STPC pin's status as LED2 output or STPC output. The MODE0.4 bit defines the trigger pin's debounce time as long debounce (50 mS) or short debounce (400 uS). The MODE0.2 bit defines the behavior of the STPA/BUSY pin as STPA output in normal mode or BUSY signal output in CPU mode. The bits 5, 3, 1 and 0 are don't care bits.
5.1.2
MODE1 Register
DESCRIPTION X LED Flash type LED1 section control 3 2 LED2 control LED1 volume control Don't care 1: Alternate 0: Synchronous 4 1: YES 0: NO 1: SECTION control 0: STPC control 1: OFF 0: ON DEFINITION
BIT 7, 6, 1, 0 5
MODE1.5 is for LED flash type control. MODE1.4 is for LED1 section control ON/OFF. MODE1.3 is for LED2 Section/STPC control. MODE1.2 is for LED1 volume control.
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W523AXXX
5.1.3
BIT PAGE -
PAGE Register
7 6 5 4 PG4 3 PG3 2 PG2 1 PG1 0 PG0
The bits 0 ~ 4 in PAGE register are used for page selection. Once the page mode being defined (referring to the below section of "Option Control Function"), the working page is selected by the bits 0 ~ 4 in the PAGE register. Hence, the user can execute "LD PAGE, value" instruction to change the working page of the voice entry group. Not all of the bits 0 ~ 4 of PAGE register are used in different page mode. They are listed as below table: PAGE MODE 1-page 8-page 16-page 32-page PG4 x x x PG3 x x PG2 x PG1 x PG0 x
Where "x" means dont care and "" means must be set properly.
5.1.4
BIT EN0 EN1
EN Register (W523A012 ~ W523A120)
7 X X 6 X X 5 TG2R TG6R 4 TG1R TG5R 3 X X 2 X X 1 TG2F TG6F 0 TG1F TG5F
EN Register (W523A008, W523A010) BIT EN0 7 TG4R 6 TG3R 5 TG2R 4 TG1R 3 TG4F 2 TG3F 1 TG2F 0 TG1F
EN0 or EN1 is an 8-bit register that stores the rising/falling edge enable or disable status information for all trigger pins, which determines whether each trigger pin is retriggerable, non-retriggerable, overwrite, or non-overwrite. The 8-bit structure of this register and the rising or falling edge of the triggers corresponding to each bit are shown above. "X" indicates a "don't care" bit. The TG1, 2, 5, 6 represents triggers 1, 2, 5 and 6 respectively; the "R" represents the rising edge; and "F" represents the falling edge. When any one of the eight bits is set to "1", the rising or falling edge of the corresponding trigger pin can be enabled, interrupting the current state.
5.1.5
BIT
STOP Register
7 X 6 X 5 X 4 STE 3 STD 2 STC 1 STB 0 STA
STOP
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W523AXXX
The STOP register stores stop output status information to determine the voltage level of each stop output pin. The 8-bit structure of this register and the stop output pin corresponding to each bit are show as above table. The "X" indicates a "don't care" bit. When a particular STOP bit is set to "1", the corresponding stop signal will be an active high output.
5.1.6
R0-R3 Registers
These four registers are 8-bit register that stores the entry values of from 0 to 255 voice groups. R0 is a special register that can be incremented by "INC" instruction.
5.2
Option Control Function
There are four types of option control in W523AXXX. They can be determined by a declaration in the users program file, but cannot be controlled by register.
FUNCTION MASK OPTION DECLARATION DEFPAGE 1 Page mode configuration Operation mode Oscillator frequency Voice output type DEFPAGE 8 DEFPAGE 16 DEFPAGE 32 NORMAL CPU OSC_3MHz OSC_1.5MHz VOUT_DAC VOUT_PWM DEFINITION 256 interrupt vector/label for 1 page, 1 page in total (1-page mode) 256 interrupt vector/label for 1 page, 8 pages in total (8-page mode) 128 interrupt vector/label for 1 page, 16 pages in total (16-page mode) 64 interrupt vector/label for 1 page, 32 pages in total (32-page mode) Normal mode operation CPU mode operation 3 MHz oscillator 1.5 MHz oscillator DAC (AUD) output PWM output
"DEFPAGE" determines the page operation mode in W523AXXX. The default setting of the page mode is 1-page mode. The 8-page, 16-page or 32-page mode can be declared to extend the voice group entry from 256 to 2047 in PowerSpeech program. The W523AXXX can communicate with an external microprocessor through the simple serial CPU interface, which is the same as the W583Sxx series. The CPU interface consists of the TG1, TG2, and STPA/BUSY pins. "NORMAL" and "CPU" decide whether the operation mode of W523AXXX will be normal mode or CPU mode. "OSC_3MHz" and "OSC_1.5MHz" select the frequency of the system clock. "VOUT_DAC" and "VOUT_PWM" select the voice output type.
5.3
Interrupt Vector Allocation
The W523AXXX provides a total of 4 trigger inputs to communicate with the outside world. Each trigger pin can invoke 2 dedicate interrupt vectors depending on TG pins' status (rising or falling). The table below shows the relationship between triggers' status and interrupt vectors.
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W523AXXX
For W523A008 and W523A010: INTERRUPT VECTOR 0 1 2 3 INTERRUPT VECTOR 4 5 6 7 32 TRIGGER SOURCE TG1F TG2F TG3F TG4F TRIGGER SOURCE TG1R TG2R TG3R TG4R POI
For W523A012 ~ W523A120: INTERRUPT VECTOR 0 1 8 9 INTERRUPT VECTOR 4 5 12 13 32 TRIGGER SOURCE TG1F TG2F TG5F TG6F TRIGGER SOURCE TG1R TG2R TG5R TG6R POI
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W523AXXX
5.4 CPU Interface
The W523AXXX can communicate with an external microprocessor through a simple serial CPU interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:
Debounced OK. to clear the internal CPU counter for preventing the system from running away. (TG1F should be disabled.)
TG1 (Data) TG2 (Clock) STPA/Busy AUD/SPK+
Notes:
TDEB TCRD
END
1. TDEB means the "Debounce time". 2. TCRD is the "CPU Reset Delay" time. This should be more than 2.6 S. 3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.
Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is dependent on the MSB of data output on TG1 (Data) pin. If MSB is "1", Busy will rise after the last rising edge of TG2 (Clock) pin. If MSB is "0", Busy will rise after the rising edge that TG1 (Data) returns to high.
7 bits
TG1 (DATA) TG2 (CLK) BUSY
MSB=0
7 bits
TG1 (DATA)
MSB=1
40ns
TG2 (CLK) BUSY
40ns
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W523AXXX
To place the W523AXXX in CPU mode, program the code according to the following example. W523A015 CPU; Reserved word, used as a directive to notify the compiler for post processing. LED1 FREQ2 POI: LD MODE0,XX1XX0XXB ;bit2=0 BUSY LD EN0, 0x00 H5+voice1+T5 END 34: ; Direct trigger or CPU interrupt. H5+voice2+T5 END
The defaulted operating mode in W523AXXX is normal mode (or manual trigger mode), which is identified by the "Normal" and "CPU" option control. To enter the CPU mode, the "CPU" declaration must be inserted in the declaration region of program (*.out). In CPU mode, the bit MODE0.2, which is defined as STPA or BUSY selection for the STPA/BUSY pin, will be selected as "0" (BUSY output) automatically by the compiler unless otherwise specified explicitly by the STPA directive. The CPU, STPA, and BUSY directives can appear only in the first paragraph of the *.out files so that the compiler will automatically interpret them as Stop definitions in the POI interrupt vector. If these directives are placed elsewhere, an error message will be issued during the compilation process. In the program example shown above, the external C will transfer one byte data "34" to W523AXXX. The number 34 (Decimal) is equal to 00100010b (Binary). The interface timing is shown below.
LSB
MSB
TG1 (Data) TG2 (Clock)
<1> <2>
<3>
0
1
0
0
0
1
0
0
<4>
TDEB
TCRD
<1> When TG1 is pulled low, the W523AXXX stops playing voice or executing instruction and waits for data from the external C. <2> If TG1 is debounced OK, the W523AXXX will clear the CPU receiving buffer. <3> 8-bit data are transferred by TG1 (Data) and TG2 (Clock). LSB is sent firstly. <4> TG1 returns to high and starts the CPU interrupt service. In this case W523A015 will play the H51+voice2+T51 sections and the STPA/BUSY pin is pulled high during the playing period.
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W523AXXX
The TG1 pin, which is pulled high with a 500K resistor, should be kept high during non-transmission periods to reduce power consumption. The external C should be connected to the W523AXXX by an inverted-type output port for better noise immunity. In CPU mode, the W523AXXX stops operating upon the falling edge of the TG1 pin. For the CPU interface to work normally, TG1F should be disabled. Thus, one suggestion is that TG1F, TG1R, TG2F, and TG2R should all be disabled in CPU mode. The master frequency of the external C, and hence the clock rate of TG1 and TG2, tends to vary among different vendors and applications. Note: In CPU mode application, in case the last voice group entry point, 255, is no used, it should be typed "END" command to avoid abnormal operating. Instruction Set List There are two types of instruction in the W523AXXX, unconditional and conditional instructions. The first types of instructions are executed immediately after they are issued. The second types of instructions are executed only when the conditions specified in the instruction are satisfied. All the instructions are listed in the following table. The cycle time for each instruction is 2/Sampling Frequency (Fs). For example, Fs = 6.0 KHz, the cycle time is 333 S. JP JP LD LD LD LD LD LD END MV INC Legend: G: Interrupt vector/label Rn: R0-R3 Rm: R0-R3 MODEi: MODE0, MODE1 value: 8-bit data @STS can be the following: @LAST, @TGn_HIGH, @TGn_LOW, n = 1-4 (W523A008, W523A010), n = 1,2,5,6 (W523A012~A120). Rn, Rm UNCONDITIONAL G Rn EN0, value EN1, value MODEi, value STOP, value PAGE, value Rn, value JP JP LD LD LD LD LD LD END MV INC Rn, Rm CONDITIONAL G Rn EN0, value EN1, value MODEi, value STOP, value PAGE, value Rn, value @STS @STS @STS @STS @STS @STS @STS @STS @STS @STS @STS
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W523AXXX
6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
SYMBOL VDD-VSS VIN TSTG TOPR CONDITIONS All Inputs RATED VALUE -0.3 to +7.0 VSS -0.3 to VDD +0.3 -55 to +150 0 to +70 UNIT V V C C PARAMETER Power Supply Input Voltage Storage Temp. Operating Temp.
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
6.2
DC Characteristics
PARAMETER SYM. VDD VIL VIH ISB1 VDD = 3V, All I/O pins unconnected, No Playing VDD = 5V, All I/O pins unconnected, No Playing VDD = 3V, No Load VDD = 5V, No Load VDD = 3V, Vin = 0V VDD = 3V, Vin = 3V VDD = 3V, Vin = 0V VDD = 4.5V, Rl = 100 VDD = 3V, Vout = 0.4V VDD = 3V, Vout = 2.7V VDD = 3V, Rl = 8 -4.0 0.8 -0.8 100 -100 -5.0 CONDITIONS DAC output PWM output MIN. 2.4 2.4 VSS -0.3 0.7 x VDD TYP. 3.0 3.0 MAX. 5.5 5.5 0.3 x VDD VDD 1 1 500 1 -8 30 -8 -6.0 A A A mA A A A mA mA mA mA mA UNIT V V V
(TA = 25 C, VSS = 0V)
Operating Voltage Input Voltage
Standby Current ISB2 Operating Current (Ring type) Input Current of TG pins Input Current of TEST pin Input Current of SEL, RESET SPK (D/A Full Scale) Output Current of STPA-STPE Output Current of SPK+, SPKIOP1 IOP2 IIN1 IIN2 IIN3 IDAC IOL1 IOH1 IOL2 IOH2
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W523AXXX
6.3 AC Characteristics
PARAMETER Oscillation Frequency (W58300 ICE chip) Oscillation Frequency (W523AXXX production chip) Oscillation Frequency Deviation by Voltage Drop Instruction Cycle Time POI Delay Time Long Debounce Time Short Debounce Time Fosc2 Fosc2 Fosc2 Tins TPD TDEBL TDEBS SYM. Fosc1 CONDITIONS Ring oscillator, Rosc = 270 K Ring oscillator, Rosc = 560 K Ring Oscillator, Rosc = 750 K Ring Oscillator, Rosc = 1.6 M F(3V)-F(2.4V) F(3V) Fosc = 3 MHz, SR = 6 KHz Fosc = 3 MHz Fosc = 3 MHz, SR = 6 KHz 50 400 1/3 160 MIN. 2.7 1.3 2.7 1.3 TYP. 3 1.5 3 1.5 MAX. 3.3 1.7 3.3 1.7 7.5 UNIT MHz MHz MHz MHz % mS mS mS S
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W523AXXX
7. BONDING PAD DIAGRAM
(For W523A008 and W523A010 only)
(0,0)
21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PAD NO. 1 2 3 4 5 6 7 8 9 10 11
PAD NAME VDD OSC X TEST
RESET
PAD NO. 12 13 14 15 16 17 18 19 20 21 -
PAD NAME LED1 STPA/BUSY STPB LED2/STPC STPD STPE VSS1 VDD1 SPKAUD/SPK+ -
TG1 TG2 TG3 TG4 VSS NC
NC means "No Connection"
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W523AXXX
(For W523A012 ~ W523A120)
(0,0)
1 2 3 4 5 28 29
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
27
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PAD NAME VDD OSC NC NC TEST
RESET
PAD NO. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 -
PAD NAME NC LED1 STPA/BUSY STPB LED2/STPC STPD STPE NC NC NC VSS1 VDD1 SPKAUD/SPK+ -
TG1 TG2 NC NC TG5 TG6 NC NC VSS
NC: means "No Connection"
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W523AXXX
8. TYPICAL APPLICATION CIRCUIT
8.1 DAC Output
VDD (2.4V ~ 5.5V)
VDD Rosc OSC TEST
VDD1 LED1 STPA/BUSY STPB
LED
100 ohm
LED
100 ohm
TG1 TG2 TG5 TG6
LED2/STPC
W523AXXX
STPD STPE
Speaker 8 ohm 1/4 watt
AUD/SPK+ SPKNPN T'x Cs Rs
/RESET VSS
VSS1
Notes: 1. In principle, the playing speed determined by Rosc should correspond to the sampling rate during the coding phase. The playing speed may be adjusted by varing Rosc, however. 2. Rs is an optional current-dividing resistor. If Rs is added, the resistance should be between 390 and 820 ohm. 3. The typical Rosc = 750 Kohm for 3 MHz Fosc; and Rosc = 1.6 Mohm for 1.5 MHz Fosc. 4. Cs is optional. 5. The DC current gain of the NPN transistor ranges from 120 to 200. 6. All unused trigger pins can be left open because of their internal pull-high resistance. 7. The OSC layout in customer's PCB should be as closed as the OSC pad to avoid noise coupling. 8. The chip's substrate must be wired to Vss. 9. W523A008~A010's trigger pins are TG1, TG2, TG3, TG4; W523A012~W523A120's trigger pins are TG1, TG2, TG5, TG6.
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W523AXXX
8.2 PWM Output
VDD (2.4V ~ 5.5V)
0.1uF~10 uF VDD Rosc OSC TEST VDD1 LED1 STPA/BUSY STPB TG1 TG2 TG5 TG6 LED2/STPC LED 100 ohm LED 100 ohm
W523AXXX
STPD STPE
AUD/SPK+ SPK-
Speaker 8 ohm 1/4 watt
/RESET VSS
VSS1
Notes: 1. In principle, the playing speed determined by Rosc should correspond to the sampling rate during the coding phase. The playing speed may be adjusted by varing Rosc, however. 2. The typical Rosc = 750 Kohm for 3 MHz Fosc; and Rosc = 1.6 Mohm for 1.5 MHz Fosc. 3. The capacity, 0.1uF~10 uF, is necessary to reduce voltage fluctuation while PWM outputting. 4. All unused trigger pins can be left open because of their internal pull-high resistance. 5. The OSC layout in customer's PCB should be as closed as the OSC pad to avoid noise coupling. 6. The chip's substrate must be wired to Vss. 7. W523A008~A010's trigger pins are TG1, TG2, TG3, TG4; W523A012~W523A120's trigger pins are TG1, TG2, TG5, TG6.
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W523AXXX
9. REVISION HISTORY
VERSION A1 A2 DATE Dec. 1, 2001 Feb. 6, 2002 EDITOR Steven Lin Steven Lin Initial Issued Page 1, line 6, "14 kinds of bodies" numbers". Page1, line 7, Note: "by 6.4K..." A3 May 20, 2003 Steven Lin "14 kinds of part "by various..." DESCRIPTION
Page 11, ROSC = 750 Kohm for 3 MHz Page 11, ROSC = 1.6 Mohm for 1.5 MHz
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: May 20, 2003 Revision A3

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